SSGTRGAF=0, SSELCB=0, SSCAFBL=0, SSGTRGBF=0, SSELCC=0, SSCBRAL=0, SSELCA=0, SSCARBL=0, SSCBFAH=0, SSELCD=0, SSGTRGBR=0, SSGTRGAR=0, CSTRT=0, SSCAFBH=0, SSCBRAH=0, SSCARBH=0, SSCBFAL=0
General PWM Timer Start Source Select Register
| SSGTRGAR | GTETRGA Pin Rising Input Source Counter Start Enable 0 (0): Counter start is disable at the rising edge of GTETRGA input 1 (1): Counter start is enable at the rising edge of GTETRGA input |
| SSGTRGAF | GTETRGA Pin Falling Input Source Counter Start Enable 0 (0): Counter start is disable at the falling edge of GTETRGA input 1 (1): Counter start is enable at the falling edge of GTETRGA input |
| SSGTRGBR | GTETRGB Pin Rising Input Source Counter Start Enable 0 (0): Counter start is disable at the rising edge of GTETRGB input 1 (1): Counter start is enable at the rising edge of GTETRGB input |
| SSGTRGBF | GTETRGB Pin Falling Input Source Counter Start Enable 0 (0): Counter start is disable at the falling edge of GTETRGB input 1 (1): Counter start is enable at the falling edge of GTETRGB input |
| Reserved | These bits are read as 0000. The write value should be 0000. |
| SSCARBL | GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 0 (0): Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 1 (1): Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 |
| SSCARBH | GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 0 (0): Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 1 (1): Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 |
| SSCAFBL | GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 0 (0): Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 1 (1): Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 |
| SSCAFBH | GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 0 (0): Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 1 (1): Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 |
| SSCBRAL | GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 0 (0): Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 1 (1): Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 |
| SSCBRAH | GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 0 (0): Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 1 (1): Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 |
| SSCBFAL | GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 0 (0): Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 1 (1): Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 |
| SSCBFAH | GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 0 (0): Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 1 (1): Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 |
| SSELCA | ELC_GPTA Event Source Counter Start Enable 0 (0): Counter start is disable at the ELC_GPTA input 1 (1): Counter start is enable at the ELC_GPTA input |
| SSELCB | ELC_GPTB Event Source Counter Start Enable 0 (0): Counter start is disable at the ELC_GPTB input 1 (1): Counter start is enable at the ELC_GPTB input |
| SSELCC | ELC_GPTC Event Source Counter Start Enable 0 (0): Counter start is disable at the ELC_GPTC input 1 (1): Counter start is enable at the ELC_GPTC input |
| SSELCD | ELC_GPTD Event Source Counter Start Enable 0 (0): Counter start is disable at the ELC_GPTD input 1 (1): Counter start is enable at the ELC_GPTD input |
| Reserved | These bits are read as 00000000000. The write value should be 00000000000. |
| CSTRT | Software Source Counter Start Enable 0 (0): Counter start is disable by the GTSTR register 1 (1): Counter start is enable by the GTSTR register |